1. Field of the Invention
This invention relates to a semiconductor circuit, and more particularly to an amplifier circuit for amplifying a voltage signal.
2. Description of the Related Art
Conventional amplifier circuits are utilized in various portions of semiconductor circuits.
FIG. 1 is a circuit diagram showing an example of a conventional level-shifting circuit for shifting the level of a signal from the ECL level to the CMOS level. Referring to FIG. 1, input ECL signal V.sub.IN is inputted to the base of bipolar transistor Q.sub.21, and the emitter terminal of transistor Q.sub.21 is grounded to the lowest potential (hereinafter referred to as ground potential) GND by way of current source I.sub.21, thereby constituting emitter follower circuit EF21. Output signal V.sub.IN1 of emitter follower circuit EF21 is inputted to level-shifting circuit LC21. Signal V.sub.IN1 is inputted to the gate of a P-type MOS field effect transistor (hereinafter referred to as a PMOS FET) M.sub.21, the source of which is connected to the highest potential (hereinafter referred to as the power supply voltage) V.sub.CC. The drain of PMOS FET M.sub.21 is connected to the drain and the gate of an N-type MOS field effect transistor (hereinafter referred to as a NMOS FET) M.sub.23. The source of NMOS FET M.sub.23 is connected to ground potential GND, and the gate of NMOS FET M.sub.23 is connected commonly to the gate of NMOS FET M.sub.24, whereby an NMOS current mirror circuit is constituted from NMOS FETs M.sub.23 and M.sub.24. Input signal V.sub.IN1 is inputted also to the source of PMOS FET M.sub.22, the drain of which is connected to the drain of NMOS FET M.sub.24, whereby a CMOS inverter is constituted from MOS FETs M.sub.22 and M.sub.24. The drain terminals of PMOS FET M.sub.22 and NMOS FET M.sub.24 make an output terminal of level-shifting circuit LC21. Constant voltage V.sub.R21 for establishing a reference is applied to the gate of PMOS FET M.sub.22.
In operation, signal V.sub.IN1 is level shifted by emitter follower circuit EF21 to a suitable input level voltage which normally presents a high level V.sub.CC -V.sub.f or a low level V.sub.CC -V.sub.f -.DELTA.V, where V.sub.f is a forward voltage of the pn junction and is about 0.8 V, and .DELTA.V is a signal amplitude and is about 0.5 to 1.5 V. When the level of signal V.sub.IN1 is changed to the low level, PMOS FET M.sub.21 and NMOS FET M.sub.24 are turned ON via the NMOS current mirror circuit, but PMOS FET M.sub.22 is turned OFF when V.sub.R21 is equal to V.sub.CC -V.sub.f -.DELTA.V-V.sub.TP, where V.sub.TP is the threshold voltage level of the PMOS FETs. The threshold voltage level of NMOS FETs is represented by V.sub.TN. Consequently, output signal out of the drains of PMOS FET M.sub.22 and NMOS FET M.sub.24 drops to the ground potential GND. On the other hand, when the level of signal V.sub.IN1 is changed to the high level if voltage V.sub.f is V.sub.f =V.sub.TP, PMOS FET M.sub.21 and NMOS FETs M.sub.23 and M.sub.24 are turned OFF, and PMOS FET M.sub.22 is turned ON. Consequently, output signal V.sub.out rises to V.sub.out =V.sub.IN1 =V.sub.CC -V.sub.f (refer to ISSCC Digest Of Technical Papers, 1989, p32).
FIG. 2 is a circuit diagram of an example of a conventional sensing amplifier circuit for amplifying a read-out small amplitude signal of a memory circuit. Referring to FIG. 2, input signal V.sub.INO which is an operating input signal and another signal V.sub.INOi which is opposite in phase to signal V.sub.INO are signals having an amplitude of approximately 0.5 to 2 V. Signal V.sub.INO is received by the gate of PMOS FET M.sub.31, and opposite phase signal V.sub.INOi is received by the gate of PMOS FET M.sub.32. A pair of NMOS FETs, M.sub.33 and M.sub.34, which form a current mirror circuit are connected to the drains of PMOS FETs M.sub.31 and M.sub.32, respectively. Here, the NMOS FET M.sub.33 side serves for current monitoring while the NMOS FET M.sub.34 side serves for driving, and the CMOS outputs of PMOS FET M.sub.32 and NMOS FET M.sub.34 produce output signal V.sub.out. A similar circuit wherein the inputs of signals V.sub.INO and V.sub.INOi to the PMOS gates are reversed is formed from PMOS and NMOS FETs M.sub.35 to M.sub.38 and the output of the circuit is signal V.sub.outi, which is opposite in phase to signal V.sub.out. A PMOS FET to which an input signal of the low level is inputted is turned up, but a PMOS FET to which an input signal of the high level is inputted is either turned ON at a low level or is turned OFF. Since the level to which PMOS FETs M.sub.31 and M.sub.35 are turned ON is transmitted in proportion to the level to which NMOS FETs M.sub.34 and M.sub.38 are turned ON due to an effect of the NMOS current mirror circuit, when the level of signal V.sub.INO is high and the level of opposite phase signal V.sub.INOi is low, output signal V.sub.out is raised to V.sub.out =V.sub.CC by PMOS FET M.sub.32 while opposite phase signal V.sub.outi is lowered to V.sub.outi =GND by NMOS FET M.sub.38. This similarly applies in cases in which the inputs are reversed.
Various modifications have also been reported including a sensing amplifier circuit of the same type wherein the transistor which receives an input signal at the gate thereof is formed from an NMOS FET or the current mirror circuit is formed from PMOS FETs (refer to the ISSCC 1990 Digest Of Technical Papers 1990, P134).
In the conventional amplifier circuits described above, since a current mirror circuit is employed, when high-speed operation is required, the responding speed of the current mirror circuit must be high. To this end, the capacities to which the transistors are turned ON on the raising side and the lowering side for receiving input signals must be raised. While the turning on capacity can be raised by adjusting the voltage of the input signal to increase the gate voltage, the turning off capacity is also increased simultaneously, and this results in the increase of through currents and the reduction of the turning ON/OFF ratio. This causes saturation in the increase of the speed and the reduction of the voltage margin arising from an increase of power consumption and a decrease of the amplifying capacity (gain). This is becoming a serious problem in designing high-speed integrated circuits.
Further, in the conventional circuits described above, if the types and/or the switching operation types of the transistors on the raising side and the lowering side for receiving input signals are different, individually optimum input voltages are involved. However, in actual use, signals are inputted at the same voltage to the transistors, and as a result, the conventional circuits fail to exhibit sufficient device performance.
The problems described above are expected to become more serious with the development of larger scale, high-speed integrated circuits.